IEEE

Improving DRAM performance by parallelizing refreshes with accesses

Abstract: Modern DRAM cells are periodically refreshed to prevent data loss due to leakage. Commodity DDR (double data rate) DRAM refreshes cells at the rank level. This degrades performance ...
IEEE

Multi-standard low-power DDR I/O circuit design in 7nm CMOS process

Abstract: This paper presents novel circuit techniques to implement DDR I/O circuit design that can support multiple low-power standards in a state-of-art 7nm CMOS finfet process. Hybrid pull-up ...