Semiconductor Engineering

LLMs In The High-Level Synthesis Design Flow

A new technical paper titled “Are LLMs Any Good for High-Level Synthesis?” was published by researchers at University of Arizona. Abstract “The increasing complexity and demand for faster, ...
EDN

High-level synthesis package speeds design

The Synphony HLS high-level synthesis package integrates M-language and model-based synthesis and is said to yield up to 10 times higher design and verification productivity than traditional RTL flows ...
Semiconductor Engineering

Ensure Equivalence Of Synthesizable C++/SystemC Designs Against Generated/Handwritten RTL

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this ...
EDN

Synthesis needs to change to serve modern chip design

As EDA tools evolve, the resulting products try to increase automation. Unfortunately, the last great advance was from schematics to language-based design starting with the first synthesis tools in ...