SoC sub-components (IPs) generally come from various sources – internal and external – and with that it has become necessary that designers ensure the RTL is testable. If the RTL has testability ...

All power optimization tools can perform combinational optimization, where there is an opportunity to gate a register clock input, based on the combinational logic that is feeding the register’s data ...

With the increasing complexity of SoCs, multiple and independent clocks are essential in the design. The design specifications require system level muxing of some of these clocks before they are sent ...